UCC27517DBVT

The UCC27516 and UCC27517 single-channel, high-speed, low-side gate driver devices can effectively drive MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC27516 and UCC27517 can source and sink high peak-current pulses into capacitive loads offering rail-to-rail drive capability and extremely small propagation delay, typically 13 ns.

The UCC27516 and UCC27517 provides 4-A source, 4-A sink (symmetrical drive) peak-drive current capability at VDD = 12 V.

The UCC27516 and UCC27517 are designed to operate over a wide VDD range of 4.5 to 18 V and wide temperature range of –40°C to 140°C. Internal undervoltage lockout (UVLO) circuitry on the VDD pin holds output low outside VDD operating range. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging wide band-gap power-switching devices such as GaN power semiconductor devices.

The UCC27516 and UCC27517 devices feature a dual-input design which offers flexibility of implementing both inverting (IN– pin) and noninverting (IN+ pin) configurations with the same device. Either the IN+ or IN– pin can be used to control the state of the driver output. The unused input pin can be used for enable and disable function. For safety purpose, internal pullup and pulldown resistors on the input pins ensure that outputs are held low when input pins are in floating condition. Hence the unused input pin is not left floating and must be properly biased to ensure that driver output is in enabled for normal operation.

The input pin threshold of the UCC27516 and UCC27517 devices are based on TTL and CMOS compatible low-voltage logic which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

Key Features

• Low-Cost Gate-Driver Device Offering Superior Replacement
  of NPN and PNP Discrete Solutions
• 4-A Peak-Source and 4-A Peak-Sink Symmetrical Drive
• Fast Propagation Delays (13-ns Typical)
• Fast Rise and Fall Times (9-ns and 7-ns Typical)
• 4.5 to 18-V Single-Supply Range
• Outputs Held Low During VDD UVLO (Ensures Glitch-Free
  Operation at Power Up and Power Down)
• TTL and CMOS Compatible Input-Logic Threshold (Independent
  of Supply Voltage)
• Hysteretic-Logic Thresholds for High-Noise Immunity
• Dual Input Design (Choice of an Inverting (IN– pin) or
  Noninverting (IN+ Pin) Driver Configuration)
  • Unused Input Pin Can Be Used for Enable or Disable Function
• Output Held Low When Input Pins Are Floating
• Input Pin Absolute Maximum Voltage Levels Not Restricted
  by VDD Pin Bias Supply Voltage
• Operating Temperature Range of –40°C to 140°C
• 5-Pin DBV (SOT-23) and 6-Pin DRS (3-mm ×
  3-mm WSON With Exposed Thermal Pad) Package Options

Application

• Power Management
• Signal Processing
• Alternative Energy
• Motor Drive & Control