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NT5CB256M16CP-DI

4Gb DDR3 SDRAM C-Die

Inventory:5,194

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Overview of NT5CB256M16CP-DI

DescriptionThe 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM containing 4,294,967,296 bits. It is internally configured as an octal-bank DRAM. Features●JEDEC DDR3 Compliant- 8n Prefetch Architecture- Differential Clock(CK/CK) and Data Strobe(DQS/DQS)- Double-data rate on DQs, DQS and DM●Data Integrity- Auto Self Refresh (ASR) by DRAM built-in TS- Auto Refresh and Self Refresh Modes●Power Saving Mode- Partial Array Self Refresh (PASR)'- Power Down Mode●Signal IntegrityConfigurable DS for system compatibility- Configurable On-Die Termination- ZQ Calibration for DS/ODT impedance accuracy viaexternal ZQ pad (240 ohm土1%)●Signal Synchronization- Write Leveling via MR settings- Read Leveling via MPR●Interface and Power Supply- SSTL_ 15 for DDR3:VDD/VDDQ=1.5V(40.075V)- SSTL_ 135* for DDR3L:VDD/VDDQ=135V(-0.067/+0.1V)

Key Features

  • JEDEC DDR3 Compliant- 8n Prefetch Architecture- Differential Clock(CK/CK) and Data Strobe(DQS/DQS)- Double-data rate on DQs, DQS and DMData Integrity- Auto Self Refresh (ASR) by DRAM built-in TS- Auto Refresh and Self Refresh ModesPower Saving Mode- Partial Array Self Refresh (PASR)'- Power Down ModeSignal IntegrityConfigurable DS for system compatibility- Configurable On-Die Termination- ZQ Calibration for DS/ODT impedance accuracy viaexternal ZQ pad (240 ohm±1%)Signal Synchronization- Write Leveling via MR settings- Read Leveling via MPRInterface and Power Supply- SSTL_ 15 for DDR3:VDD/VDDQ=1.5V(40.075V)- SSTL_ 135 for DDR3L:VDD/VDDQ=135V(-0.067/+0.1V)

Specifications

The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.

Rohs Code Yes Part Life Cycle Code Obsolete
Ihs Manufacturer NANYA TECHNOLOGY CORP Package Description TFBGA, BGA96,9X16,32
Reach Compliance Code compliant ECCN Code EAR99
HTS Code 8542.32.00.36 Access Mode MULTI BANK PAGE BURST
Access Time-Max 0.225 ns Additional Feature AUTO/SELF REFRESH
Clock Frequency-Max (fCLK) 800 MHz I/O Type COMMON
Interleaved Burst Length 8 JESD-30 Code R-PBGA-B96
Length 13 mm Memory Density 4294967296 bit
Memory IC Type DDR3 DRAM Memory Width 16
Number of Functions 1 Number of Ports 1
Number of Terminals 96 Number of Words 268435456 words
Number of Words Code 256000000 Operating Mode SYNCHRONOUS
Operating Temperature-Max 85 °C Operating Temperature-Min
Organization 256MX16 Output Characteristics 3-STATE
Package Body Material PLASTIC/EPOXY Package Code TFBGA
Package Equivalence Code BGA96,9X16,32 Package Shape RECTANGULAR
Package Style GRID ARRAY, THIN PROFILE, FINE PITCH Peak Reflow Temperature (Cel) NOT SPECIFIED
Power Supplies 1.5 V Qualification Status Not Qualified
Refresh Cycles 8192 Seated Height-Max 1.2 mm
Self Refresh YES Sequential Burst Length 8
Standby Current-Max 0.018 A Supply Current-Max 0.3 mA
Supply Voltage-Max (Vsup) 1.575 V Supply Voltage-Min (Vsup) 1.425 V
Supply Voltage-Nom (Vsup) 1.5 V Surface Mount YES
Technology CMOS Temperature Grade OTHER
Terminal Form BALL Terminal Pitch 0.8 mm
Terminal Position BOTTOM Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED
Width 9 mm

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