KSZ9131MNXI

By incorporating on-chip termination resistors for differential pairs and integrating an LDO controller for core power supply, the KSZ9131MNXI reduces board cost and simplifies layout design. This innovative approach not only enhances performance but also streamlines the production process, saving time and resources for manufacturers

Key Features

• Single-chip 10/100/1000Mbps IEEE 802.3 compliant Ethernet transceiver
• GMII/MII/RGMII with 3.3V/2.5V/1.8V tolerant I/Os
• Auto-negotiation to automatically select the highest linkup speed (10/100/1000Mbps) and duplex (half/full)
• On-chip termination resistors for the differential pairs
• On-chip LDO controller to support single 3.3V supply operation – requires only one external FET to generate 1.2V for the core
• Jumbo frame support up to 16KB
• 125MHz Reference Clock Output
• Energy-detect power-down mode for reduced power consumption when the cable is not attached
• Wake-on-LAN (WOL) support with robust custom-packet detection
• Programmable LED outputs for link, activity, and speed
• Baseline wander correction
• LinkMD® TDR-based cable diagnostic to identify faulty copper cabling
• Parametric NAND tree support to detect faults between chip I/Os and board
• Loopback modes for diagnostics
• Automatic MDI/MDI-X crossover to detect and correct pair swap at all speeds of operation
• MDC/MDIO management interface for PHY register configuration
• Automatic detection and correction of pair swaps, pair skew, and pair polarity
• Interrupt pin option
• Power-down and power-saving modes
• Operating voltages: Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator) VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V Transceiver (AVDDH): 3.3V or 2.5V (commercial temp)
• Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V (external FET or regulator)
• VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
• Transceiver (AVDDH): 3.3V or 2.5V (commercial temp)
• Available in 48-pin QFN (7mm x 7mm) and 64-pin QFN (8mm x 8mm) packages