• GAL22V10D-25LPNI 24-PDIP
GAL22V10D-25LPNI 24-PDIP

GAL22V10D-25LPNI

SPLD - Simple Programmable Logic Devices HI PERF E2CMOS PLD

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Overview of GAL22V10D-25LPNI

GAL®22V10 Programmable Logic Device (PLD) IC 10 Macrocells 24-PDIP

Key Features

  • HIGH PERFORMANCE E2CMOS® TECHNOLOGY
  • — 4 ns Maximum Propagation Delay
  • — Fmax = 250 MHz
  • — 3.5 ns Maximum from Clock Input to Data Output
  • — UltraMOS® Advanced CMOS Technology
  • ACTIVE PULL-UPS ON ALL PINS
  • COMPATIBLE WITH STANDARD 22V10 DEVICES
  • — Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS 22V10 Devices
  • 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
  • — 90mA Typical Icc on Low Power Device
  • — 45mA Typical Icc on Quarter Power Device
  • E2 CELL TECHNOLOGY
  • — Reconfigurable Logic
  • — Reprogrammable Cells
  • — 100% Tested/100% Yields
  • — High Speed Electrical Erasure (<100ms)
  • — 20 Year Data Retention
  • TEN OUTPUT LOGIC MACROCELLS
  • — Maximum Flexibility for Complex Logic Designs
  • PRELOAD AND POWER-ON RESET OF REGISTERS
  • — 100% Functional Testability
Lattice Semiconductor Corporation Inventory

Specifications

The followings are basic parameters of the part selected concerning the characteristics of the part and categories it belongs to.

Pbfree Code Yes Rohs Code Yes
Part Life Cycle Code Obsolete Ihs Manufacturer LATTICE SEMICONDUCTOR CORP
Part Package Code DIP Package Description DIP, DIP24,.3
Pin Count 24 Reach Compliance Code
HTS Code 8542.39.00.01 Samacsys Manufacturer Lattice Semiconductor
Additional Feature 10 MACROCELLS; SHARED INPUT/CLOCK Architecture PAL-TYPE
Clock Frequency-Max 33.3 MHz JESD-30 Code R-PDIP-T24
JESD-609 Code e3 Length 31.75 mm
Moisture Sensitivity Level 1 Number of Dedicated Inputs 11
Number of I/O Lines 10 Number of Inputs 22
Number of Outputs 10 Number of Product Terms 132
Number of Terminals 24 Operating Temperature-Max 85 °C
Operating Temperature-Min -40 °C Organization 11 DEDICATED INPUTS, 10 I/O
Output Function MACROCELL Package Body Material PLASTIC/EPOXY
Package Code DIP Package Equivalence Code DIP24,.3
Package Shape RECTANGULAR Package Style IN-LINE
Peak Reflow Temperature (Cel) NOT SPECIFIED Power Supplies 5 V
Programmable Logic Type EE PLD Propagation Delay 25 ns
Qualification Status Not Qualified Seated Height-Max 5.334 mm
Supply Voltage-Max 5.5 V Supply Voltage-Min 4.5 V
Supply Voltage-Nom 5 V Surface Mount NO
Technology CMOS Temperature Grade INDUSTRIAL
Terminal Finish Matte Tin (Sn) Terminal Form THROUGH-HOLE
Terminal Pitch 2.54 mm Terminal Position DUAL
Time@Peak Reflow Temperature-Max (s) NOT SPECIFIED Width 7.62 mm

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